XSBench on FPGAs using Intel oneAPI
| Authors | |
|---|---|
| Year of publication | 2024 |
| Type | Article in Proceedings |
| Conference | EPJ Web of Conferences |
| MU Faculty or unit | |
| Citation | |
| Web | https://www.epj-conferences.org/articles/epjconf/abs/2024/12/epjconf_snamc2024_04007/epjconf_snamc2024_04007.html |
| Doi | http://dx.doi.org/10.1051/epjconf/202430204007 |
| Keywords | FPGA;XSBench;particle simulator;high level synthesis;benchmark;HLS |
| Description | Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature. The current generation of FPGAs includes specialized hard blocks for floating point operations, making them attractive for scientific computing. FPGA programming has historically been done in hardware description languages, which required a deep understanding of hardware design. Emerging high-level synthesis tools, such as Intel oneAPI and AMD Vitis™, provide a more common programming environment for FPGAs. In this paper, we explore the capabilities of FPGAs for acceleration in the context of nuclear particle transport simulators. As a case study, we implement XS-Bench in Intel oneAPI targeting FPGAs, including basic optimizations. We then compare the performance of Intel Stratix10 FPGA and Intel Xeon CPU-based systems and evaluate the viability of FPGA use in heterogeneous systems. |
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