Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.
| Authors | |
|---|---|
| Year of publication | 2019 |
| Type | Article in Periodical |
| Magazine / Source | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| MU Faculty or unit | |
| Citation | |
| Web | http://dx.doi.org/10.1109/TVLSI.2019.2923848 |
| Doi | http://dx.doi.org/10.1109/TVLSI.2019.2923848 |
| Keywords | Testing; Cryptography; Field programmable gate arrays; Hardware; System-on-chip; Generators; Machine learning |
| Description | Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for the randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for the automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the algebraic normal form. The randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip that integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance, and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer. |
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