Fault Collapsing and Test Generation for a Circuit

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Authors

AMIRI Moslem PŘENOSIL Václav

Year of publication 2013
Type Article in Proceedings
Conference Deterioration, Dependability, Diagnostics 2013
MU Faculty or unit

Faculty of Informatics

Citation
Field Informatics
Keywords fault list generation; test vector generation; fault paths
Attached files
Description A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s) for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.
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